Verilog计数器中增减操作之资源占用示例

安路Anlogic TD Release_2026.1_SP2器件选择EG4A20BG256方法1case语句module test( input clk,input rst_n,input sw,output reg [3:0] led ); always (posedge clk or negedge rst_n) if (!rst_n) led 0; else begin case (sw) 1: ledled1; default: ledled-1; endcase end endmodule方法2if语句module test( input clk,input rst_n,input sw,output reg [3:0] led ); always (posedge clk or negedge rst_n) if (!rst_n) led 0; else begin if (sw)ledled1; else ledled-1; end endmodule方法3条件运算符? :module test( input clk,input rst_n,input sw,output reg [3:0] led ); always (posedge clk or negedge rst_n) if (!rst_n) led 0; else begin ledsw?(led1):(led-1); end endmodule方法42*sw-1module test( input clk,input rst_n,input sw,output reg [3:0] led ); always (posedge clk or negedge rst_n) if (!rst_n) led 0; else begin ledled2*sw-1; end endmodule资源占用比较方法4占用资源最少方法notDFFMACRO_ADDMACRO_MUXlut4lut5case242331if242331? :2423312*sw-1142031