Verilog计数器中增减操作之资源占用示例
安路Anlogic TD Release_2026.1_SP2,器件选择:EG4A20BG256方法1)case语句module test( input clk,input rst_n,input sw,output reg [3:0] led );always (posedge clk or negedge rst_n)if (!rst_n) led< 0; else begin case (sw)1: led…
2026/9/26 11:00:14